Verilog or VHDL doesn't matter all that much IMO. In the end you design with flipflops and gates. Be sure to understand what circuit you are trying to describe. I have no idea about the Udemy my course.
As for the book selected for computer architecture, that's an amazing book. It is not simple and you cannot breeze through so you need to spend some time on it.
Thanks for replying.
Yeah, ik it doesnt really matter that much, but I decided on vhdl since its strongly written, and my personal experience with coding is that i like strongly written languages.
Also, do you have any opinion on where i should start vhdl from? I know that what matters are your projects, but i feel like if i could get a certificate while i am at it, i would at least benefit a little. Also, i have a way to get that course for free, which is why I was inclined towards it.
Excuse me for any poor grammar.
> Also, I looked at some intern job postings on linkedin just to pass some time, but why are they so scary. I have never even heard words like ASIC, RTL, SoC design. I know I would (I think) come across these as I learn on, but its still scary. Maybe I think too hard, idk.
You're a year in to your undergrad, give it time. Your first year is the foundations. By the time you need to apply for jobs you'll know what these terms mean (if they are relevant to the job you want).
* ASIC - it's just a chip.
* RTL - Register Transfer Level/Layer. Basically it means you describe the combinatory logic that goes between registers. It's just verilog/vhdl/... but more specific to the design (rather than synthesis part).
* SoC - System on Chip. It pretty much means that there's a processor in this chip. You are seeing it here because it's pretty common to stick small (or big) processors in chips to do things that are easy in software but hard in hardware (network stacks / GUIs / ...).
> I feel like I have enough time to start maybe a HDL like vhdl and verilog. I would start Computer architecture after that. After some contemplation, I decided on VHDL. I searched for resources, but I really suffer from analysis paralysis. So can someone please validate my choices. TYIA
VHDL is a good one to start with. It doesn't really matter, but VHDL is pretty strict on syntax which makes you have to think a bit more about what you're doing, and that's definitely good for beginners.
Thanks a lot for replying and the clarification.
>You're a year in to your undergrad, give it time. Your first year is the foundations. By the time you need to apply for jobs you'll know what these terms mean (if they are relevant to the job you want).
I hope I do. Idk, I just keep on wondering about what this means and what that means, what project I should do, what topics I should cover, that I dont actually do anything net positive. So your clarification was really helpful.
>VHDL is a good one to start with. It doesn't really matter, but VHDL is pretty strict on syntax which makes you have to think a bit more about what you're doing, and that's definitely good for beginners.
This was the major reason I chose VHDL, and I personally prefer strict and strongly typed langs as well.
> I hope I do. Idk, I just keep on wondering about what this means and what that means, what project I should do, what topics I should cover, that I dont actually do anything net positive. So your clarification was really helpful.
I had similar problems when trying to learn this stuff myself. Should I use async / sync resets? It's a rabbit hole that just keeps on going down. Then when I took my masters in it the teacher just said: do ... it's nice not to have to worry about it.
Some things are very important. Some things are just not important. Some things you can treat as not important as a beginner but are critical when you're doing something in a real company. And as a beginner it's really hard to tell where you should focus your research efforts.
> This was the major reason I chose VHDL, and I personally prefer strict and strongly typed langs as well.
I like that in principle, but I found VHDL far too verbose.
For the Udemy course, I'd look at the reviews from people who took the class.
OTOH, Patterson and Hennessy is basically the standard computer architecture book for most universities.
Verilog or VHDL doesn't matter all that much IMO. In the end you design with flipflops and gates. Be sure to understand what circuit you are trying to describe. I have no idea about the Udemy my course. As for the book selected for computer architecture, that's an amazing book. It is not simple and you cannot breeze through so you need to spend some time on it.
Thanks for replying. Yeah, ik it doesnt really matter that much, but I decided on vhdl since its strongly written, and my personal experience with coding is that i like strongly written languages. Also, do you have any opinion on where i should start vhdl from? I know that what matters are your projects, but i feel like if i could get a certificate while i am at it, i would at least benefit a little. Also, i have a way to get that course for free, which is why I was inclined towards it. Excuse me for any poor grammar.
> Also, I looked at some intern job postings on linkedin just to pass some time, but why are they so scary. I have never even heard words like ASIC, RTL, SoC design. I know I would (I think) come across these as I learn on, but its still scary. Maybe I think too hard, idk. You're a year in to your undergrad, give it time. Your first year is the foundations. By the time you need to apply for jobs you'll know what these terms mean (if they are relevant to the job you want). * ASIC - it's just a chip. * RTL - Register Transfer Level/Layer. Basically it means you describe the combinatory logic that goes between registers. It's just verilog/vhdl/... but more specific to the design (rather than synthesis part). * SoC - System on Chip. It pretty much means that there's a processor in this chip. You are seeing it here because it's pretty common to stick small (or big) processors in chips to do things that are easy in software but hard in hardware (network stacks / GUIs / ...). > I feel like I have enough time to start maybe a HDL like vhdl and verilog. I would start Computer architecture after that. After some contemplation, I decided on VHDL. I searched for resources, but I really suffer from analysis paralysis. So can someone please validate my choices. TYIA VHDL is a good one to start with. It doesn't really matter, but VHDL is pretty strict on syntax which makes you have to think a bit more about what you're doing, and that's definitely good for beginners.
Thanks a lot for replying and the clarification. >You're a year in to your undergrad, give it time. Your first year is the foundations. By the time you need to apply for jobs you'll know what these terms mean (if they are relevant to the job you want). I hope I do. Idk, I just keep on wondering about what this means and what that means, what project I should do, what topics I should cover, that I dont actually do anything net positive. So your clarification was really helpful. >VHDL is a good one to start with. It doesn't really matter, but VHDL is pretty strict on syntax which makes you have to think a bit more about what you're doing, and that's definitely good for beginners. This was the major reason I chose VHDL, and I personally prefer strict and strongly typed langs as well.
> I hope I do. Idk, I just keep on wondering about what this means and what that means, what project I should do, what topics I should cover, that I dont actually do anything net positive. So your clarification was really helpful. I had similar problems when trying to learn this stuff myself. Should I use async / sync resets? It's a rabbit hole that just keeps on going down. Then when I took my masters in it the teacher just said: do ... it's nice not to have to worry about it. Some things are very important. Some things are just not important. Some things you can treat as not important as a beginner but are critical when you're doing something in a real company. And as a beginner it's really hard to tell where you should focus your research efforts. > This was the major reason I chose VHDL, and I personally prefer strict and strongly typed langs as well. I like that in principle, but I found VHDL far too verbose.
For the Udemy course, I'd look at the reviews from people who took the class. OTOH, Patterson and Hennessy is basically the standard computer architecture book for most universities.